1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, it relates to a method of manufacturing a semiconductor memory device capable of preventing soft errors caused by radioactive rays such as alpha rays.
2. Description of the Prior Art
A dynamic RAM (Random Access Memory) which stores data depending on presence or absence of stored charges has been known as a semiconductor memory device.
FIG. 1 is a cross sectional view showing a structure of a peripheral portion of a memory cell in a 250K dynamic RAM as an example of such a conventional semiconductor memory device.
Description is now made on the structure of the peripheral portion of the memory cell shown in FIG. 1.
In FIG. 1, a p.sup.+ -type region 10 for preventing inversion and parasitism is formed on a p.sup.- -type semiconductor substrate 1, and an insulator film 9 for isolating elements is formed on the p.sup.+ -type region 10. In addition, a p.sup.+ -type region 11 having higher impurity concentration, by one figure, than that of the substrate 1 is formed on the p.sup.- -type semiconductor substrate 1, and an n.sup.+ -type region 6 serving as a charge storage region for storing data is formed on the p.sup.+ -type region 11. Furthermore, a first gate insulator film 4 is formed on the n.sup.+ -type region 6 and an insulator film 9, and a first gate electrode 2 connected to a power supply (not shown) through a terminal 20 is formed on the first gate insulator film 4. The n.sup.+ -type region 6, the first gate insulator film 4 and the first gate electrode 2 constitute a memory cell.
Additionally, an n.sup.+ -type region 80a serving as one source/drain region is formed in communication with the n.sup.+ -type region 6 on the p.sup.- -type semiconductor substrate 1, and an n.sup.+ -type region 81a serving as the other source/drain region is formed apart from the n.sup.+ -type region 80a. The n.sup.+ -type region 81a is connected to a bit line (not shown) and has a downward convex portion 7 in the center of the bottom portion. The convex portion serves to prevent the bit line from breaking through the bottom face of the n.sup.+ -type region 81a and reaching the p.sup.- -type semiconductor substrate 1 when the bit line comes into contact with the n.sup.+ -type region 81a. A second gate insulator film 5a is formed on the p.sup.- -type semiconductor substrate 1 between the n.sup.+ -type regions 80a and 81a, an end of the n.sup.+ -type region 80a and an end of the n.sup. + -type region 81a, and a second gate electrode 3a connected to a word line (not shown) through a terminal 30 in formed on the second gate insulator film 5a. The p.sup.- -type semiconductor substrate 1, the n.sup.+ -type region 80a, the n.sup.+ -type region 81a, the second gate insulator film 5a and the second gate electrode 3a constitute a transfer gate transistor.
For simplicity of illustration, an interlayer insulation film formed on the n.sup.+ -type region 80a, the second gate electrode 3a and the n.sup.+ -type region 81a, interconnection portions such as a bit line formed on the interlayer insulation film and a protective film formed on the interlayer insulation film and the interconnection portions are omitted in FIG. 1. Furthermore, instead of forming the n.sup.+ -type region 6 serving as an impurity diffusion region, a positive potential may be applied to the first gate electrode 2 to induce an n.sup.+ -type inversion layer in the portion on the p.sup.- -type semiconductor substrate 1 corresponding to the n.sup.+ -type region 6, thereby to store charges therein.
Description is now made on the operation of the peripheral portion of the memory cell shown in FIG. 1.
In the semiconductor memory device shown in FIG. 1, a state in which electrons are stored in the n.sup.+ -type region 6 serving as a charge storage region in the memory cell is defined as "0" and a state in which electrons are not stored therein is defined as "1". The potential of the n.sup.+ -type region 81a connected to a bit line (not shown) is held at a predetermined intermediate level by a sense amplifier (not shown).
When the potential of a word line is increased and the potential of the second gate electrode 3a in the transfer gate transistor connected to the word line exceeds the threshold voltage, a channel of an n.sup.+ -type inversion layer is formed directly under the second gate electrode 3a, whereby the channel is rendered conductive between the n.sup.+ -type regions 6 and 80a and the n.sup.+ -type region 81a.
If and when storage data of the memory cell is "0", that is, when electrons are stored in the n.sup.+ -type region 6, the potential of the n.sup.+ -type region 81a, which has been so far held at an intermediate level, is decreased by conduction between the n.sup.+ -type regions 6 and 80a and the n.sup.+ -type region 81a connected to a bit line. On the other hand, when storage data of the memory cell is "1", that is, when electrons are not stored in the n.sup.+ -type region 6, the potential of the n.sup.+ -type region 81a, which has been so far held at an intermediate level, is increased by that conduction. Such potential change of the bit line is sensed by the sense amplifier so that the same is amplified and extracted, while the same storage data is refreshed to be rewritten in the memory cell in the same cycle.
In the conventional semiconductor memory device shown in FIG. 1, since the source/drain region and the charge storage region are formed of an n.sup.+ -type region or an n.sup.+ -type inversion layer, electrons out of electron-hole pairs generated upon incidence of radioactive rays such as alpha rays into a memory chip are collected in the n.sup.+ -type regions 6 and 80a and the n.sup.+ -type region 81a, so that there occurs malfunctions (referred to as soft errors hereinafter) in which original storage data is inverted.
A method for preventing soft errors induced by such alpha rays is disclosed in, for example, an article by George A. Sai-Halasz et al., entitled "Alpha-Particle-Induced Soft Error Rate in VLSI Circuits", IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. ED-29, No. 4, April, 1982, pp. 725-731.
In order to solve the above described problem, means for preventing soft errors has been known by forming the p.sup.+ -type region 11 to come into contact with the n.sup.+ -type region 6 serving as a charge storage region, to increase memory cell capacitance, that is, critical charge capacitance so that malfunctions may not be caused even if electrons generated by radioactive rays such as alpha rays are generated in the n.sup.+ -type region 6. However, the n.sup.+ -type region 80a and the n.sup.+ -type region 81a connected to a bit line is not protected from collection of electrons, and soft errors in a bit line mode depending on the cycle time of memory operation are still caused.
If p.sup.+ -type regions are additionally provided around the n.sup.+ -type regions 80a and 81a, the p.sup.+ -type regions are arranged opposed to each other within a narrow spacing to cause operation of a parasitic pnp transistor, so that it becomes difficult to operate the transfer gate transistor stably.